1. Field of the Invention
The present invention relates generally to a precise and programmable duty cycle generator which employs multiple duty cycle generators connected in series to provide multiple duty cycle tap point outputs, each with a different known and precise duty cycle and each having precisely phase aligned leading or trailing edges.
Almost all ICs require a clock signal to accomplish their operations and be synchronous with other related components. The frequency of this clock determines the performance of the IC. As sub-micron technologies allow designs to operate at higher frequencies, design techniques must also provide for increasing their performance. An adjustable duty cycle clock circuit provides designers with flexibility in their designs, allowing them to meet high-performance and low-power goals. In addition to this flexibility, a programmable duty cycle adjuster provides robustness to the design. After fabrication, if the process was not modeled accurately, the duty cycle can be adjusted through the IC bus, fuses, or primary pins on the IC to operate the IC at the highest possible clock rate.
In a clocking system, phase aligned clock signals are imperative. Generally a PLL is used to generate an on-chip clock signal of the desired frequency from a reference clock oscillator of lower frequency. The PLL ensures that the output clock signal is phase aligned with respect to the input reference clock oscillator.
A prior disclosure, filed as U.S. patent application Ser. No. 10/020,528, filed on even date herewith and titled, xe2x80x9cA Precise And Programmable Duty Cycle Generatorxe2x80x9d, is hereby expressly incorporated by reference herein and describes a circuit to generate/create a user definable duty cycle with precision from an input signal having any duty cycle, and is described with reference to FIGS. 1-5 herein. As explained in that disclosure, for a fixed number of delay stages the range of duty cycle selection is inversely proportional to the frequency of the signal at CLKIN.
A prior disclosure, filed as U.S. patent application Ser. No. 10/017,071, filed on even date herewith, and entitled xe2x80x9cEnhanced Operational Frequency for a Precise and Programmable Duty Cycle Generatorxe2x80x9d, is hereby expressly incorporated by reference herein and describes a circuit to further enhance the operation frequency range and precision of the previously disclosed circuit configuration for producing a user definable duty cycle with precision. That scheme allows the precise and programmable duty cycle circuit to support a wider range of frequencies and duty cycle sensitivities which are now selectable. Applications wherein the incoming frequency is variable or selectable can readily employ this approach and have the desired output duty cycle without loss of precision.
A prior disclosure, filed as U.S. patent application Ser. No. 10/020,533, filed on even date herewith, and titled xe2x80x9cMultiple Duty Cycles Tap Points For A Precise And Programmable Duty Cycle Generatorxe2x80x9d, is hereby expressly incorporated by reference herein and describes a circuit to generate multiple different duty cycles from any input duty cycle, and is described with reference to FIGS. 1-8 herein.
Pursuant to the present invention, the duty cycle generation schemes of the prior disclosures are employed in concert with a PLL to produce the desired duty cycle signal. The various tap points of the multiple duty cycles as disclosed in U.S. patent application Ser. No. 10/020,533, filed Dec. 14, 2001, are precise with respect to the desired duty cycle, but are shifted in time and phase with respect to each other, and the present invention precisely phase aligns the leading or trailing edges of the multiple duty cycle signals.
2. Discussion of the Prior Art
The idea of providing a circuit for duty cycle correction isn""t new. The prior art has circuits which correct an incoming signal""s duty cycle to a fixed value, typically 50xe2x80x9450. The present invention differs from the prior art by allowing the output corrected signal to be programmable to any value duty cycle with precision.
Most prior art circuits provide only 50/50 duty cycles without the ability to provide other duty cycles. U.S. Pat. No. 4,881,041 discloses a circuit to correct an incoming signal""s duty cycle to a 50/50 duty cycle, and is limited to a 50/50 duty cycle correction with no provision for any other duty cycle, and the circuit is completely different from the present invention. U.S. Pat. No. 5,157,277 discloses a circuit to convert a sine wave input clock signal at a 50/50 duty cycle into a square wave signal with a variable duty cycle. The conversion circuit is limited to sine wave inputs, and is significantly different from the present invention which addresses square wave signals.
Accordingly, it is a primary object of the present invention to provide a precise programmable duty cycle generator which employs multiple duty cycle generators connected in series to provide multiple duty cycle tap point outputs, each with a known and precise value of a duty cycle from a source input signal having any duty cycle, and which aligns the leading edges or trailing edges of multiple duty cycle tap point output signals from a programmable duty cycle generator.
The present invention transforms an incoming signal""s duty cycle to a known value by a first programmable duty cycle generator, and then applies the output of the first programmable duty cycle generator to a second programmable duty cycle generator which provides multiple duty cycle tap point outpoints, each having a different known value of a precise duty cycle, wherein the leading edges or trailing edges of the multiple duty cycle tap point output signals are phase aligned with respect to each other.
The present invention generates multiple concurrent duty cycle output signals with precision from an input signal having any duty cycle, and further provides that each of the multiple and programmable duty cycle tap point output signals are phase aligned with respect to each other and the source input signal.